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? 1 ? e01504b41 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. ICX418ALL 20 pin dip (cer-dip) diagonal 8mm (type 1/2) ccd image sensor for eia b/w video cameras description the ICX418ALL is an interline ccd solid-state image sensor suitable for eia b/w video cameras with a diagonal 8mm (type 1/2) system. compared with the current product icx038dla, basic characteristics such as sensitivity, smear, dynamic range and s/n are improved drastically. this chip features a field period readout system and an electronic shutter with variable charge-storage time. this chip is compatible with the pins of the icx038dla and has the same drive conditions. features ? high sensitivity (+5.0db compared with the icx038dla) low smear (?5.0db compared with the icx038dla) high d range (+2.0db compared with the icx038dla) high s/n high resolution and low dark current excellent antiblooming characteristics continuous variable-speed shutter substrate bias: adjustment free (external adjustment also possible with 6 to 14v) reset gate pulse: 5vp-p adjustment free (drive also possible with 0 to 9v) horizontal register: 5v drive device structure interline ccd image sensor optical size: diagonal 8mm (type 1/2) number of effective pixels: 768 (h) 494 (v) approx. 380k pixels total number of pixels: 811 (h) 508 (v) approx. 410k pixels chip size: 7.40mm (h) 5.95mm (v) unit cell size: 8.4m (h) 9.8m (v) optical black: horizontal (h) direction: front 3 pixels, rear 40 pixels vertical (v) direction: front 12 pixels, rear 2 pixels number of dummy bits: horizontal 22 vertical 1 (even fields only) substrate material: silicon optical black position (top view) 2 12 v h pin 1 pin 11 40 3
? 2 ? ICX418ALL use restriction notice (december 1, 2003 ver.) this use restriction notice ("notice") is for customers who are considering or currently using the ccd products ("products") set forth in this specifications book. sony corporation ("sony") may, at any time, modify this notice which will be available to you in the latest specifications book for the products. you should abide by the latest version of this notice. if a sony subsidiary or distributor has its own use restriction notice on the products, such a use restriction notice will additionally apply between you and the subsidiary or distributor. you should consult a sales representative of the subsidiary or distributor of sony on such a use restriction notice when you consider using the products. use restrictions the products are intended for incorporation into such general electronic equipment as office products, communication products, measurement products, and home electronics products in accordance with the terms and conditions set forth in this specifications book and otherwise notified by sony from time to time. you should not use the products for critical applications which may pose a life- or injury- threatening risk or are highly likely to cause significant property damage in the event of failure of the products. you should consult your sony sales representative beforehand when you consider using the products for such critical applications. in addition, you should not use the products in weapon or military equipment. sony disclaims and does not assume any liability and damages arising out of misuse, improper use, modification, use of the products for the above-mentioned critical applications, weapon and military equipment, or any deviation from the requirements set forth in this specifications book. design for safety sony is making continuous efforts to further improve the quality and reliability of the products; however, failure of a certain percentage of the products is inevitable. therefore, you should take sufficient care to ensure the safe design of your products such as component redundancy, anti-conflagration features, and features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social damage as a result of such failure. export control if the products are controlled items under the export control laws or regulations of various countries, approval may be required for the export of the products under the said laws or regulations. you should be responsible for compliance with the said laws or regulations. no license implied the technical information shown in this specifications book is for your reference purposes only. the availability of this specifications book shall not be construed as giving any indication that sony and its licensors will license any intellectual property rights in such information by any implication or otherwise. sony will not assume responsibility for any problems in connection with your use of such information or for any infringement of third-party rights due to the same. it is therefore your sole legal and financial responsibility to resolve any such problems and infringement. governing law this notice shall be governed by and construed in accordance with the laws of japan, without reference to principles of conflict of laws or choice of laws. all controversies and disputes arising out of or relating to this notice shall be submitted to the exclusive jurisdiction of the tokyo district court in japan as the court of first instance. other applicable terms and conditions the terms and conditions in the sony additional specifications, which will be made available to you when you order the products, shall also be applicable to your use of the products as well as to this specifications book. you should review those terms and conditions when you consider purchasing and/or using the products.
? 3 ? ICX418ALL block diagram and pin configuration (top view) 11 12 13 14 15 16 17 18 19 20 note) : photo sensor nc v dsub nc gnd gnd rd rg nc h 1 h 2 10 9 8 7 6 5 4 3 2 1 v out v dd gnd v l v 1 gnd sub v 2 v 3 v 4 note) horizontal register vertical register pin description pin no. pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 symbol description v 4 v 3 v 2 sub gnd v 1 v l gnd v dd v out vertical register transfer clock vertical register transfer clock vertical register transfer clock substrate clock gnd vertical register transfer clock protective transistor bias gnd output circuit supply voltage signal output symbol description nc v dsub nc gnd gnd rd rg nc h 1 h 2 substrate bias circuit supply voltage gnd gnd reset drain bias reset gate clock horizontal register transfer clock horizontal register transfer clock
? 4 ? ICX418ALL absolute maximum ratings item substrate clock sub ? gnd supply voltage clock input voltage voltage difference between vertical clock input pins voltage difference between horizontal clock input pins h 1 , h 2 ? v 4 rg ? gnd rg ? sub v l ? sub pins other than gnd and sub ? v l storage temperature operating temperature ?0.3 to +50 ?0.3 to +18 ?55 to +10 ?15 to +20 to +10 to +15 to +17 ?17 to +17 ?10 to +15 ?55 to +10 ?65 to +0.3 ?0.3 to +30 ?30 to +80 ?10 to +60 v v v v v v v v v v v v c c ? 1 ratings unit remarks ? 1 +27v (max.) when clock width < 10s, clock duty factor < 0.1%. v dd , v rd , v dsub , v out ? gnd v dd , v rd , v dsub , v out ? sub v 1 , v 2 , v 3 , v 4 ? gnd v 1 , v 2 , v 3 , v 4 ? sub
? 5 ? ICX418ALL dc characteristics output circuit supply current item i dd symbol 5.0 min. unit remarks typ. max. ma 10.0 bias conditions 1 [when used in substrate bias internal generation mode] output circuit supply voltage reset drain voltage protective transistor bias substrate bias circuit supply voltage substrate clock ? 1 v l setting is the v vl voltage of the vertical transfer clock waveform, or the same supply voltage as the v l power supply for the v driver should be used. (when cxd1267an is used.) ? 2 do not apply a dc bias to the substrate clock pin, because a dc bias is generated within the ccd. item v dd v rd v l v dsub sub symbol 15.0 15.0 ? 1 15.0 ? 2 min. v v v unit remarks typ. max. 14.55 14.55 14.55 15.45 15.45 15.45 v rd = v dd bias conditions 2 [when used in substrate bias external adjustment mode] output circuit supply voltage reset drain voltage protective transistor bias substrate bias circuit supply voltage substrate voltage adjustment range substrate voltage adjustment precision ? 3 v l setting is the v vl voltage of the vertical transfer clock waveform, or the same supply voltage as the v l power supply for the v driver should be used. (when cxd1267an is used.) ? 4 connect to gnd or leave open. ? 5 the setting value of the substrate voltage (v sub ) is indicated on the back of the image sensor by a special code. when adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage. the adjustment precision is 3%. however, this setting value has not significance when used in substrate bias internal generation mode. v sub code ? one character indication code and optimal setting correspond to each other as follows. item v dd v rd v l v dsub v sub ? v sub symbol 15.0 15.0 ? 3 ? 4 min. v v v % unit remarks typ. max. 14.55 14.55 6.0 ?3 15.45 15.45 14.0 +3 v rd = v dd ? 5 ? 5 "l" v sub = 9.0v v sub code optimal setting f 6.5 g 7.0 h 7.5 j 8.0 k 8.5 l 9.0 m 9.5 n 10.0 p 10.5 q 11.0 s 12.0 u 13.0 v 13.5 w 14.0 r 11.5 t 12.5 e 6.0
? 6 ? ICX418ALL clock voltage conditions ? 1 input the reset gate clock without applying a dc bias. in addition, the reset gate clock can also be driven with the following specifications. readout clock voltage vertical transfer clock voltage horizontal transfer clock voltage reset gate clock voltage ? 1 substrate clock voltage item v vt v vh1 , v vh2 v vh3 , v vh4 v vl1 , v vl2 , v vl3 , v vl4 v v | v vh1 ? v vh2 | v vh3 ? v vh v vh4 ? v vh v vhh v vhl v vlh v vll v h v hl v rgl v rg v rglh ? v rgll v sub symbol 14.55 ?0.05 ?0.2 ?9.6 8.3 ?0.25 ?0.25 4.75 ?0.05 4.5 23.0 min. 1 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 waveform diagram v vh = (v vh1 + v vh2 )/2 v vl = (v vl3 + v vl4 )/2 v v = v vh n ? v vl n (n = 1 to 4) high-level coupling high-level coupling low-level coupling low-level coupling low-level coupling remarks reset gate clock voltage item v rgl v rg symbol 4 4 waveform diagram remarks 15.0 0 0 ?9.0 9.0 5.0 0 ? 1 5.0 24.0 ty p. 15.45 0.05 0.05 ?8.5 9.65 0.1 0.1 0.1 0.5 0.5 0.5 0.5 5.25 0.05 5.5 0.8 25.0 max. unit v v v v vp-p v v v v v v v vp-p v v vp-p v vp-p ?0.2 8.5 min. 0 9.0 ty p. 0.2 9.5 max. unit v vp-p
? 7 ? ICX418ALL horizontal transfer clock equivalent circuit vertical transfer clock equivalent circuit h 1 h 2 c h1 c h2 c hh v 1 c v12 v 2 v 4 v 3 c v34 c v23 c v41 c v1 c v2 c v4 c v3 r gnd r 4 r 1 r 3 r 2 clock equivalent circuit constant c v1 , c v3 c v2 , c v4 c v12 , c v34 c v23 , c v41 c h1 c h2 c hh c rg c sub r 1 , r 3 r 2 , r 4 r gnd symbol capacitance between vertical transfer clock and gnd capacitance between vertical transfer clocks capacitance between horizontal transfer clock and gnd capacitance between horizontal transfer clocks capacitance between reset gate clock and gnd capacitance between substrate clock and gnd vertical transfer clock series resistor vertical transfer clock ground resistor item min. 2700 2700 820 330 100 91 47 11 680 91 100 68 ty p. max. pf pf pf pf pf pf pf pf pf ? ? ? unit remarks
? 8 ? ICX418ALL drive clock waveform conditions (1) readout clock waveform (2) vertical transfer clock waveform v vh = (v vh1 + v vh2 )/2 v vl = (v vl3 + v vl4 )/2 v v = v vh n ? v vl n (n = 1 to 4) 100% 90% 10% 0% tr tf 0v twh m 2 m v vt v vh1 v vhh v vhl v vh v vlh v vl1 v vll v vhl v vhh v vl v vhh v vh v vlh v vll v vl v vhl v vl3 v vhl v vh3 v vhh v vh2 v vhh v vhh v vhl v vhl v vh v vlh v vl2 v vll v vl v vh v vl v vhl v vlh v vll v vhl v vh4 v vhh v vhh v vl4 v 1 v 3 v 2 v 4
? 9 ? ICX418ALL (3) horizontal transfer clock waveform (4) reset gate clock waveform v rglh is the maximum value and v rgll is the minimum value of the coupling waveform during the period from point a in the above diagram until the rising edge of rg. in addition, v rgl is the average value of v rglh and v rgll . v rgl = (v rglh + v rgll )/2 assuming v rgh is the minimum value during the period twh, then: v rg = v rgh ? v rgl negative overshoot level during the falling edge of rg is v rglm . (5) substrate clock waveform 100% 90% 10% 0% v sub tr tf twh m 2 m v sub tr twh tf 90% 10% twl v h v hl point a twl v rg v rgh v rgl v rglh rg waveform v rgll h 1 waveform twh tr tf +2.5v v rglm v rgl + 0.5v
? 10 ? ICX418ALL clock switching characteristics ? 1 when vertical transfer clock driver cxd1267an is used. ? 2 tf tr ? 2ns. ? 3 the overlap period for twh and twl of horizontal transfer clocks h 1 and h 2 is two. min. two typ. max. 16 20 unit ns remarks item horizontal transfer clock symbol h 1 , h 2 ? 3 min. twh ty p. max. min. typ. max. min. typ. max. min. typ. max. twl tr tf 2.3 11 1.5 2.5 20 5.38 13 1.8 20 5.38 51 15 0.01 0.01 3 19 0.5 0.5 15 15 0.01 0.01 3 250 19 0.5 unit s ns ns s ns s remarks during readout ? 1 ? 2 when draining charge item readout clock vertical transfer clock reset gate clock substrate clock symbol v t v 1 , v 2 , v 3 , v 4 h h 1 h 2 rg sub horizontal transfer clock 0.5 during imaging during parallel-serial conversion
? 11 ? ICX418ALL image sensor characteristics item sensitivity saturation signal smear video signal shading dark signal dark signal shading flicker lag symbol s ysat sm sh vdt ? vdt f lag min. 880 1000 ty p. 1100 ?115 max. ?105 20 25 2 1 2 0.5 unit mv mv db % % mv mv % % measurement method 1 2 3 4 4 5 6 7 8 remarks ta = 60c zone 0 and i zone 0 to ii' ta = 60c ta = 60c zone definition of video signal shading 14 v 10 14 12 10 ignored region effective pixel region zone 0, i zone ii, ii' v 10 h 8 h 8 768 (h) 494 (v) (ta = 25c)
? 12 ? ICX418ALL image sensor characteristics measurement method measurement conditions 1) in the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device.) 2) in the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (ob) is used as the reference for the signal output, which is taken as the value of y signal output or chroma signal output of the measurement system. definition of standard imaging conditions 1) standard imaging condition i : use a pattern box (luminance 706cd/m 2 , color temperature of 3200k halogen source) as a subject. (pattern for evaluation is not applicable.) use a testing standard lens with cm500s (t = 1.0mm) as an ir cut filter and image at f8. the luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) standard imaging condition ii : image a light source (color temperature of 3200k) with a uniformity of brightness within 2% at all angles. use a testing standard lens with cm500s (t = 1.0mm) as an ir cut filter. the luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. sensitivity set to standard imaging condition i . after selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (vs) at the center of the screen and substitute the value into the following formula. s = vs [mv] 2. saturation signal set to standard imaging condition ii . after adjusting the luminous intensity to 10 times the intensity with average value of the signal output, 200mv, measure the minimum value of the signal output. 3. smear set to standard imaging condition ii . with the lens diaphragm at f5.6 to f8, adjust the luminous intensity to 500 times the intensity with average value of the signal output, 200mv. when the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective h blankings, measure the maximum value vsm [mv] of the signal output and substitute the value into the following formula. sm = 20 log 4. video signal shading set to standard imaging condition ii . with the lens diaphragm at f5.6 to f8, adjust the luminous intensity so that the average value of the signal output is 200mv. then measure the maximum (vmax [mv]) and minimum (vmin [mv]) values of the signal output and substitute the values into the following formula. sh = (vmax ? vmin)/200 100 [%] 250 60 1 10 1 500 vsm 200 [db] (1/10v method conversion value)
? 13 ? ICX418ALL 5. dark signal measure the average value of the signal output (vdt [mv]) with the device ambient temperature 60c and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. dark signal shading after measuring 5, measure the maximum (vdmax [mv]) and minimum (vdmin [mv]) values of the dark signal output and substitute the values into the following formula. ? vdt = vdmax ? vdmin [mv] 7. flicker set to standard imaging condition ii . adjust the luminous intensity so that the average value of the signal output is 200mv, and then measure the difference in the signal level between fields ( ? vf [mv]). then substitute the value into the following formula. fy = ( ? vf/200) 100 [%] 10. lag adjust the signal output value generated by strobe light to 200mv. after setting the strobe light so that it strobes with the following timing, measure the residual signal (vlag). substitute the value into the following formula. lag = (vlag/200) 100 [%] light signal output 200mv ylag (lag) fld v1 strobe light timing output
? 14 ? ICX418ALL drive circuit 1 (substrate bias internal generation mode) 22/16v 0.01 ?9v 3.3/16v 3.3/20v 0.01 1/35v 1 100 h 1 h 2 nc rg rd gnd gnd nc v dsub nc 22/20v ccd out [ ? a] 15v xsub xv2 xv1 xsg1 xv3 xsg2 xv4 h 2 h 1 rg 100k 0.01 cxd1267an 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 3.9k v 4 v 3 v 2 sub gnd v l gnd v dd v out v 1 icx418 (bottom view) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1m
? 15 ? ICX418ALL drive circuit 2 (substrate bias external adjustment mode) 22/16v 0.01 ?9v 3.3/16v 3.3/20v 0.01 1/35v 0.1 100 h 1 h 2 nc rg rd gnd gnd nc v dsub nc 22/20v ccd out [ ? a] 15v xsub xv2 xv1 xsg1 xv3 xsg2 xv4 h 2 h 1 rg 27k 0.01 cxd1267an 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 3.9k 0.1 39k 15k 47k 15k 270k 100k 1/35v 1/35v 0.1 v 4 v 3 v 2 sub gnd v l gnd v dd v out v 1 icx418 (bottom view) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1m 56k
? 16 ? ICX418ALL spectral sensitivity characteristics (excludes lens characteristics and light source characteristics) sensor readout clock timing chart unit: s odd field even field v1 v2 v3 v4 v1 v2 v3 v4 2.5 2.5 2.5 2.5 33.5 1.6 0.2 1.0 0.8 0.9 0.6 0.4 0.2 0.7 0.5 0.3 0.1 0 400 500 600 700 wave length [nm] relative response 800 900 1000
? 17 ? ICX418ALL drive timing chart (vertical sync) 520 525 1 2 3 4 5 10 15 20 493 494 260 265 270 275 280 494 493 2 1 4 3 6 5 2 1 4 3 6 5 fld vd blk hd v1 v2 v3 v4 ccd out 135 24 6 135 246
? 18 ? ICX418ALL drive timing chart (horizontal sync) 760 768 1 2 3 5 10 20 30 40 1 2 3 5 10 20 22 1 2 3 1 2 3 10 20 hd blk h1 h2 rg v1 v2 v3 v4 sub
? 19 ? ICX418ALL notes on handling 1) static charge prevention ccd image sensors are easily damaged by static discharge. before handling be sure to take the following protective measures. a) either handle bare handed or use non-chargeable gloves, clothes or material. also use conductive shoes. b) when handling directly use an earth band. c) install a conductive mat on the floor or working table to prevent the generation of static electricity. d) ionized air is recommended for discharge when handling ccd image sensor. e) for the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) soldering a) make sure the package temperature does not exceed 80c. b) solder dipping in a mounting furnace causes damage to the glass and other defects. use a ground 30w soldering iron and solder each pin in less than 2 seconds. for repairs and remount, cool sufficiently. c) to dismount an image sensor, do not use a solder suction equipment. when using an electric desoldering tool, use a thermal controller of the zero cross on/off type and connect it to ground. 3) dust and dirt protection image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. clean glass plates with the following operation as required, and use them. a) perform all assembly operations in a clean room (class 1000 or less). b) do not either touch glass plates by hand or have any object come in contact with glass surfaces. should dirt stick to a glass surface, blow it off with an air blower. (for dirt stuck through static electricity ionized air is recommended.) c) clean with a cotton bud and ethyl alcohol if the grease stained. be careful not to scratch the glass. d) keep in a case to protect from dust and dirt. to prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) when a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. do not reuse the tape. 4) installing (attaching) a) remain within the following limits when applying a static load to the package. do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (this may cause cracks in the package.) b) if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portions. therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. 39n lower ceramic upper ceramic compressive strength low melting point glass 29n shearing strength 29n tensile strength 0.9nm torsional strength
? 20 ? ICX418ALL c) the adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) the upper and lower ceramic are joined by low melting point glass. therefore, care should be taken not to perform the following actions as this may cause cracks. applying repeated bending stress to the outer leads. heating the outer leads for an extended period with a soldering iron. rapidly cooling or heating the package. applying any load or impact to a limited portion of the low melting point glass using tweezers or other sharp tools. prying at the upper or lower ceramic using the low melting point glass as a fulcrum. note that the same cautions also apply when removing soldered products from boards. e) acrylate anaerobic adhesives are generally used to attach ccd image sensors. in addition, cyano- acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) others a) do not expose to strong light (sun rays) for long periods. for continuous using under cruel condition exceeding the normal using condition, consult our company. b) exposure to high temperature or humidity will affect the characteristics. accordingly avoid storage or usage in such conditions.
? 21 ? ICX418ALL package outline unit: mm sony corporation 0.3 m package structure package material lead treatment lead material package mass cer-dip tin plating 42 alloy 2.6g drawing number as-b14-01(e) a 1 1 0? to 9? h v c b ~ ~ 20pin dip (600mil) 20 10 11 10 11 20 (0.7r) 1.4 15.24 0.25 18.0 0.4 9.0 7.55 15.1 0.3 1.27 4.0 0.3 14.6 3 0.55 3 11.55 3 0.7 0.8 1.778 0.4 (4.0) (1.7) 1.4 (1.0) 0.70 3.26 0.3 0.46 0.4 0.51 ~ b' 1. ?a? is the center of the effective image area. 2. the two points ?b? of the package are the horizontal reference. the point ?b'? of the package is the vertical reference. 3. the bottom ?c? of the package is the height reference. 4. the center of the effective image area, relative to ?b? and ?b'? is (h, v) = (9.0, 7.55) 0.15mm. 5. the rotation angle of the effective image area relative to h and v is 1?. 6. the height from the bottom ?c? to the effective image area is 1.41 0.15mm. 7. the tilt of the effective image area relative to the bottom ?c? is less than 60m. 8. the thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 9. the notch and the hole on the bottom must not be used for reference of fixing.

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